The disclosure herein generally relates to semiconductor memory devices, and more particularly, the disclosure relates to nonvolatile semiconductor memory devices equipped with error correction code (ECC) functionality.
Semiconductor memory devices are memory devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). The semiconductor memory devices are generally classified as either volatile memory devices or nonvolatile memory devices.
Volatile memory devices are characterized by the loss of stored data when power supply thereto is interrupted. Examples of the volatile memory devices include static random-access memory (SRAM) devices, dynamic random-access memory (DRAM) devices, and synchronous dynamic random-access memory (SDRAM) devices. On the other hand, nonvolatile memory devices are characterized by the retention of stored data stored when power supply thereto is interrupted. Examples of the nonvolatile memory devices include read-only memory (ROM) devices, programmable read-only memory (PROM) devices, electrically programmable read-only memory (EPROM) devices, electrically erasable and programmable read-only memory (EEPROM) devices, flash memory devices, phase-change random-access memory (PRAM) devices, magnetic random-access memory (MRAM) devices, resistive random-access memory (RRAM) devices, and ferroelectric random-access memory (FRAM) devices. Among these, flash memory devices are generally classified as either NOR-type flash memory devices or NAND-type flash memory devices depending on connection scheme of memory cells within the devices.
In electrically erasable and programmable nonvolatile semiconductor memory devices such as EEPROM devices and flash memory devices, the operational characteristics of a memory cell degrade over time as they are subjected to repeated write/erase operations. Therefore, a memory cell may malfunction when written or erased a number of times in excess of a count limit. An error correction code (ECC) is utilized at least in part to correct an error resulting from a malfunctioning memory cell, thus effectively increasing the write/erase count limit of the memory cell.
Typically, error correction by an ECC requires a memory cell region for storing data (information bits) and a parity cell region for storing check bits (parity bits) (hereinafter, both of the two regions are referred to as an erase block). An increase in the number of parity cells may increase the number of error-correctable bits. However, the chip size may also increase with an increase in the number of parity cells. Thus, a scheme of replacing an erase block in which the number of detected error bits exceeds the number of error-correctable bits (hereinafter referred to as an ECC overflow block) with a redundant block is used to limit the number of error-correctable bits. See, for example, Japanese Patent Application Laid-Open No. 8-31196, International Patent Application Publication No. 01/022232, and Japanese Patent Application Laid-Open No. 2006-134310.